The Micro Channel architecture consists of an address bus, a data bus, an arbitration bus, a set of interrupt signals, and support signals. It uses synchronous and asynchronous procedures for data transfer between memory, I/O devices, and a controlling master. The controlling master can be a DMA controller, the system master (system processor), or a bus master. The features of the Micro Channel architecture are:
•I/O data transfers of 8-, 16-, 24-, or 32-bits within a 64KB address space (16-bit address width).
•Memory data transfers of 8-, 16-, 24-, or 32-bits within a 16MB (24-bit address width) or 4GB (32-bit address width) address space.
•A basic transfer procedure that allows data transfers between masters and slaves.
•Interrupt sharing on all levels.
•A flexible system-configuration procedure that uses programmable registers.
•Support for audio signal transfer (audio voltage-sum node).
•Support for both synchronous and asynchronous data transfer.
•An exception condition reporting procedure.
•Improved electromagnetic characteristics.
•I/O data transfers of 8-, 16-, 24-, or 32-bits within a 64KB address space (16-bit address width).
•Memory data transfers of 8-, 16-, 24-, or 32-bits within a 16MB (24-bit address width) or 4GB (32-bit address width) address space.
•A basic transfer procedure that allows data transfers between masters and slaves.
•Interrupt sharing on all levels.
•A flexible system-configuration procedure that uses programmable registers.
•Support for audio signal transfer (audio voltage-sum node).
•Support for both synchronous and asynchronous data transfer.
•An exception condition reporting procedure.
•Improved electromagnetic characteristics.
0 comments:
Post a Comment