Features Of DMA Controllers

The DMAC supports single transfers as well as a block transfer.
             •Single transfer consists of a read burst and a subsequent write burst.
             •A block transfer consists of several successive single transfers.

The data width of a transfer is programmable from 8 bits up to the data bus width in steps of powers to the base of two (8 bits, 16 bits… 1024 bits).

DMA Controllers

Direct memory access (DMA) is a feature of modern computing that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the CPU. Direct Memory Access (DMA) is one of several methods for coordinating the timing of data transfers between an input/output (I/O) device and the core processing unit or memory in a computer. An I/O device often operates at a much slower speed than the core. DMA allows the I/O device to access the memory directly, without using the core. DMA can lead to a significant improvement in performance because data movement is one of the most common operations performed in processing applications.

Interrupt Controller

     An interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution. An interrupt is a line that links the peripheral to the processor. An interrupt is a hardware interrupt when it is requested by one of the PC's hardware components. For example, this is the case when a key is touched and the keyboard wants to get the processor's attention for this event.

     Interrupt-controlled I/O reduces the severity of the two problems mentioned for program-controlled I/O by allowing the I/O device itself to initiate the device service routine in the processor. This is accomplished by having the I/O device generate an interrupt signal which is tested directly by the hardware of the CPU. When the interrupt input to the CPU is found to be active, the CPU itself initiates a subprogram call to somewhere in the memory of the processor; the particular address to which the processor branches on an interrupt depends on the interrupt facilities available in the processor.