PCI (Peripheral Component Interconnect) is a type of computer bus for attaching or inserting peripheral devices into a computer. The PCI standard was first proposed by Intel in 1990 and was widely implemented in computers by 1995. PCI allows for 32- or 64-bit bus specification. PCI is described as high-bandwidth and processor-independent data path between the CPU and high-speed peripherals. PCI uses all active paths to transmit both address and data signals, sending the address on one clock cycle and data on the next. The PCI specification defines two different card lengths. The full-size PCI form factor is 312 millimeters in long; short PCIs range from 119 to 167 millimeters in length to fit into smaller slots where space is an issue.
Showing posts with label bus. Show all posts
Showing posts with label bus. Show all posts
Thursday, August 18, 2011
Peripheral Component Interconnect (PCI)
PCI (Peripheral Component Interconnect) is a type of computer bus for attaching or inserting peripheral devices into a computer. The PCI standard was first proposed by Intel in 1990 and was widely implemented in computers by 1995. PCI allows for 32- or 64-bit bus specification. PCI is described as high-bandwidth and processor-independent data path between the CPU and high-speed peripherals. PCI uses all active paths to transmit both address and data signals, sending the address on one clock cycle and data on the next. The PCI specification defines two different card lengths. The full-size PCI form factor is 312 millimeters in long; short PCIs range from 119 to 167 millimeters in length to fit into smaller slots where space is an issue.
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Micro Channel Architecture (MCA)
The Micro Channel architecture consists of an address bus, a data bus, an arbitration bus, a set of interrupt signals, and support signals. It uses synchronous and asynchronous procedures for data transfer between memory, I/O devices, and a controlling master. The controlling master can be a DMA controller, the system master (system processor), or a bus master. The features of the Micro Channel architecture are:
•I/O data transfers of 8-, 16-, 24-, or 32-bits within a 64KB address space (16-bit address width).
•Memory data transfers of 8-, 16-, 24-, or 32-bits within a 16MB (24-bit address width) or 4GB (32-bit address width) address space.
•A basic transfer procedure that allows data transfers between masters and slaves.
•Interrupt sharing on all levels.
•A flexible system-configuration procedure that uses programmable registers.
•Support for audio signal transfer (audio voltage-sum node).
•Support for both synchronous and asynchronous data transfer.
•An exception condition reporting procedure.
•Improved electromagnetic characteristics.
•I/O data transfers of 8-, 16-, 24-, or 32-bits within a 64KB address space (16-bit address width).
•Memory data transfers of 8-, 16-, 24-, or 32-bits within a 16MB (24-bit address width) or 4GB (32-bit address width) address space.
•A basic transfer procedure that allows data transfers between masters and slaves.
•Interrupt sharing on all levels.
•A flexible system-configuration procedure that uses programmable registers.
•Support for audio signal transfer (audio voltage-sum node).
•Support for both synchronous and asynchronous data transfer.
•An exception condition reporting procedure.
•Improved electromagnetic characteristics.
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Extended Industry Standard Architecture (EISA)
EISA is a bus standard for IBM compatible computers. EISA extends the AT bus to 32 bit and allows more than one CPU to share the bus. It was much favored by manufacturers due to the proprietary nature of MCA.
Key features of the EISA bus:
ISA Compatibility: ISA cards will work in EISA slots.
32 Bit Bus Width: Like MCA, the bus was expanded to 32 bits.
Bus Mastering: The EISA bus supports bus mastering adapters for greater efficiency, including proper bus arbitration.
Plug and Play: EISA automatically configures adapter cards, similar to the Plug and Play standards of modern systems.
Key features of the EISA bus:
ISA Compatibility: ISA cards will work in EISA slots.
32 Bit Bus Width: Like MCA, the bus was expanded to 32 bits.
Bus Mastering: The EISA bus supports bus mastering adapters for greater efficiency, including proper bus arbitration.
Plug and Play: EISA automatically configures adapter cards, similar to the Plug and Play standards of modern systems.
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Industry Standard Architecture (ISA)
ISA was introduced by IBM and was originally an 8-bit computer bus that was later expanded to z 16-bit bus in 1984. when this bus was originally released it was a proprietary bus, which allowed only IBM to create peripherals and the actual interface. However, in the early 1980’s other manufacturers were creating the bus.
In 1993, Intel and Microsoft introduced a PnP ISA bus that allowed the computer to automatically detect and setup computer ISA peripherals, such as a modem or sound card.
In 1993, Intel and Microsoft introduced a PnP ISA bus that allowed the computer to automatically detect and setup computer ISA peripherals, such as a modem or sound card.
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Expansion Card or Add-in Cards
A printed circuit board that plugs into an expansion slot in a computer to provides some extra facility. The sockets normally connect to a bus, and the type of connector and the use to which each contact is put are strictly defined to ensure compatibility between the card and the computer. Cards are available that provides extra memory, communications interfaces, sound I/O capabilities, device interface to extra disks or tape backup devices for instance, or perhaps extra processors in multiprocessor systems.
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Expansion Slots
The Expansion Slots allow the computer system to communicate with the outside world. It is used for adding more memory, graphics capabilities, and support for special devices. The boards inserted into the expansion cards.
Expansion slots for PCs come in two basic sizes: half and full size. Half-size slots are also called 8-bit slots because they can transfer 8 bit at a time. Full-size are sometimes called 16-bit slots.
Expansion slots for PCs come in two basic sizes: half and full size. Half-size slots are also called 8-bit slots because they can transfer 8 bit at a time. Full-size are sometimes called 16-bit slots.
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Physical Layer Functions And Services
The physical layer is concerned with the transmission and reception of the unstructured raw bit stream over a physical medium, It describes the electrical/optical, mechanical and functional interfaces to the physical medium, and carries the signals for all of the higher layer.
The major functions and services performed by the Physical Layer are:
1.Establishment and termination of a connection to a communication medium.
2.Participation in the process whereby the communication resources are effectively shared among multiple users. For example, contention resolution and flow control.
3.Modulation, or conversion between the representation of digital data in user equipment and the corresponding signals transmitted over a communications channel. These are signals operating over the physical cabling (such as copper and optical fibers) or over a radio link.
The major functions and services performed by the Physical Layer are:
1.Establishment and termination of a connection to a communication medium.
2.Participation in the process whereby the communication resources are effectively shared among multiple users. For example, contention resolution and flow control.
3.Modulation, or conversion between the representation of digital data in user equipment and the corresponding signals transmitted over a communications channel. These are signals operating over the physical cabling (such as copper and optical fibers) or over a radio link.
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Synchronous And Asynchronous Operations
Sequential circuits are divided into two main types :-
1.Synchronous
2.Asynchronous
1.Synchronous
2.Asynchronous
- The send, receive, and reply operations may be synchronous or asynchronous. A synchronous operation blocks a process till the operation completes. An asynchronous operation is non-blocking and only initiates the operation.
- In the case of synchronous operation, a transfer of data from one point to another is assumed to occur within a fixed time interval known to both the sending and receiving devices. The sender and receiver are synchronized by a signal called the clock, which may be supplied externally to both, or generated by the sender with the data, and occasionally incorporated within it, but often sent on a separate signal line. In the case of asynchronous operation, the sending device or circuit need have no knowledge of the time-scale on which the receiver (and intervening connection) operates, but rather transmits its data with a "data ready" signal and then awaits a reply to the signal sent. Upon receipt of the reply by the sender, it removes its original data and status signal from the line, often (but not necessarily) waiting for the removal of the reply by the sender before proceeding with a second transfer.
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Serial And Parallel Models And Bus Characteristics
- A parallel link transmits several streams of data (perhaps representing particular bits of a stream of bytes) along multiple channels (wires, printed circuit tracks, optical fibers, etc.).
- A serial link transmits a single stream of data.
- A number of factors allow serial to be clocked at a greater rate:
- Clock skew between different channels is not an issue (for unlocked asynchronous links).
- A serial connection requires fewer interconnecting cables (e.g. wires/fibers) and hence occupies less space. The extra space allows for better isolation of the channel from its surroundings.
- Crosstalk is less of an issue, because there are fewer conductors in proximity.
Difference ( Comparison) Between Serial And Parallel Bus Characteristics
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Example InterConnect: Star Fabric
Three bridges could be fully interconnected with 2.5Gbps on each link. This could be used to very simply connect racks between Compact PCI chassis in a central office or POP location. In this example, no redesign would be required on existing chassis, boards or software. A front-panel or back-panel module with the Bridge could be inserted into a CPCI slot in each chassis. The chassis could then be interconnected with external shielded twisted pair cables.
To build systems with more than three bus segments a Star would be added. A small Star-based system may look like the illustration above where one Star is interconnected with 6 Bridges. Each bridge supports a full PCI bus bandwidth.
The number and types of configurations are very flexible and can be tuned by the system designer to meet the unique requirements of their application.
In telecom applications, high availability and fault tolerance are extremely important.
With Stars and Bridges, the fabric can be constructed with no single point of failure. In this example topology, a Star is added to the 6 bus segment system shown earlier. This provides redundancy on the links and the Star. If a particular path fails, packets are automatically rerouted in hardware over the remaining good path. An invalid path notification message is sent to the root node so that operations personnel can replace the faulty component.
To build systems with more than three bus segments a Star would be added. A small Star-based system may look like the illustration above where one Star is interconnected with 6 Bridges. Each bridge supports a full PCI bus bandwidth.
The number and types of configurations are very flexible and can be tuned by the system designer to meet the unique requirements of their application.
In telecom applications, high availability and fault tolerance are extremely important.
With Stars and Bridges, the fabric can be constructed with no single point of failure. In this example topology, a Star is added to the 6 bus segment system shown earlier. This provides redundancy on the links and the Star. If a particular path fails, packets are automatically rerouted in hardware over the remaining good path. An invalid path notification message is sent to the root node so that operations personnel can replace the faulty component.
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Multi Layered Protocols
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Serial Interconnect Technology
Serial interconnect technologies has matured to enable high-speed switched architectures with excellent performance and scalability, as well as low pin counts and cost. Clock speeds do jump from 33-133 MHz in the parallel connectivity world, to 2-10 GHz in the serial connectivity world. The new high-speed serial interfaces offer the lowest pin count per connection and maximum performance through a fixed number of connector pins.
Serial InterConnect Features:
Serial InterConnect Features:
- Layered protocol allowing choice of PHY for PCB, cable, or optical
- Multiple lane configurations, such as 1x, 4x, 8x, and 16x.
- Isochronous capabilities
- Split-transactions
- Flow control
- Configuration and power management
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Different Bus Standards in Computer Networking
Serial interconnects and layered protocols, Parallel models, serial models, Synchronous verses asynchronous operation, Physical layer function and services, logical sub-block, Expansion slots and Add-in cards, Bus evolution and bus wars, ISA, EISA, MCA, PCI, PCI-X, PCIe, PCMIA, Video and monitor types, Ports serial and parallel, USB and Fireware, Ethernet, Mass storage devices, Floppy and hard drives, High and low level formatting, CDs and DVDs, Types, speeds and formatting.
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